1. Field of the Invention
The present invention relates generally to comparators.
2. Description of the Related Art
FIG. 1A illustrates a conventional comparator system 20 that includes a comparator 22 which receives differential signals from an input port 23. The system also includes first and second inverters 24 and 26 that couple the differential output of the comparator 22 to a differential output port 28. Supply rail structures 30 and 32 provide bias voltages in common to the comparator 22 and inverters 24 and 26.
Various inductance sources (e.g., package, wire bonds, metal interconnects) and capacitance sources (e.g., device diffusion capacitances, interconnect-to-substrate capacitances) form parasitic inductances 34 and capacitances 36 that are positioned respectively in and across the rail structures 30 and 32. In order to reduce jitter, the comparator 22 is generally designed to exhibit a first switching threshold when its differential input signal is moving in a first relative direction and a second, different switching threshold when it is moving in a second relative direction (i.e., the comparator is designed to exhibit a predetermined hysteresis).
FIG. 1B illustrates a small-signal model of an exemplary CMOS transistor 40 that can be used in a realization of the comparator system 20 of FIG. 1A. This model shows a current source 42 which generates a current 43 of magnitude g.sub.m v.sub.gs between a source 46 and a drain 44 in which v.sub.gs is the voltage between a gate 48 and the source and gm represents the transistor's small-signal transconductance. The transistor's structure (e.g., its gate structure) causes it to exhibit a gate-to-source capacitance 52 and a gate-to-drain capacitance 50.
In a typical operation of the comparator system 20, the comparator 22 compares a differential analog signal that is applied to the input port 23 and, in response, generates a binary signal whose state corresponds to the polarity of the differential signal. The high-gain inverters 24 and 26 amplify this signal to a desired logic level (e.g., a complementary metal-oxide semiconductor (CMOS) level) which is provided at the output port 28.
The amplification process in the inverters 24 and 26 of FIG. 1A generates current impulses in the supply rail structures 30 and 32. These impulses typically react with the parasitic elements (inductances 34 and capacitances 36) to form spurious signals that are coupled back (e.g., along feedback paths 54) to the input of the comparator 22. The feedback signals are typically broadband in nature and high enough in frequency to initiate spurious conduction through current sources (42 in FIG. 1B) and capacitances (50 and 52 in FIG. 1B) of the comparator's transistors.
In addition, low-frequency components of the feedback signals alter (e.g., due to backgate effects) threshold voltages in the comparator's transistors which, in turn, alter the predetermined hysteresis of the comparator 22. Because the comparator system 20 lacks adequate noise rejection, the initiated spurious conduction and altered hysteresis effects become major noise sources of jitter, and consequent error, in the comparator system 20.